1. Field of the Invention
The present invention relates to a test pattern generator for devices with onboard memories, and more particularly to a test pattern generator and test pattern generation method which can shorten the testing process for devices having serial input functions and latch functions.
2. Description of the Related Art
In recent years, in addition to SRAMs and DRAMs, LSIs with onboard memory macros such as volatile memory and the like have been developed. These LSIs, in addition to the logic circuit macros having the prescribed logic functions such as the ALU and the like, also incorporate memory macros. When the number of external terminals is limited due to various restrictions to the LSI, the memory macro cannot be directly accessed externally, and performance testing of the memory macro cannot be conducted in shipment testing.
Performance testing has been proposed in which a serial input interface is provided within the LSI, and addresses and the like are supplied via the serial input interface during performance testing to avoid this inconvenience and permit performance testing of the memory macro. For example, as disclosed in Japanese Patent Application Laid-open No. H2-38979 (Patent Document 1).
According to the Patent Document 1, a serial input interface, and a serial-parallel conversion circuit are provided in the onboard memory in devices which can be accessed only via peripheral logic circuits, and multi-bit signals such as addresses and the like are supplied to the internal memory macro by serial input and converted to parallel signals internally.